The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), which are also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS devices or transistors. A MOS device includes a gate electrode as a control electrode and spaced apart source and drain electrodes between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel between the source and drain electrodes.
The complexity of ICs and the number of devices incorporated in ICs are continually increasing. As the number of devices in an IC increases, the size of individual devices decreases. Device size in an IC is usually noted by the minimum feature size, that is, the minimum line width or the minimum spacing that is allowed by the circuit design rules. As the semiconductor industry moves to smaller minimum feature sizes, the performance of individual devices degrades as the result of scaling. As new generations of integrated circuits and the transistors that are used to implement those integrated circuits are designed, technologists must rely heavily on non-conventional elements to boost device performance.
The performance of a MOS transistor, as measured by its current carrying capability, is proportional to the mobility of the majority carrier in the transistor channel. It is known that applying a longitudinal stress to the channel of a MOS transistor can increase the mobility; a compressive longitudinal stress enhances the mobility of majority carrier holes and a tensile longitudinal stress enhances the mobility of majority carrier electrons. It is further known that stress memorization techniques can be used to increase mobility. Specifically, structures can be used during the MOS device fabrication to impose stresses that remain, at least partially, after the structures are removed. While the use of stress memorization techniques are known, improved stress memorization techniques are desired.
Accordingly, it is desirable to optimize methods for fabricating MOS devices. In addition, it is desirable to provide an optimized method for fabricating MOS devices with a stress memorization technique that enhances stress memorization over conventional MOS device fabrication. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.